One role of a cleaning step in the fabrication of a semiconductor device is to remove contaminants. Contaminants generated while a material layer is etched have a negative influence on the operation of the device. Therefore, the contaminants should be removed.
Similarly, a fabrication process calling for a chemical mechanical polishing process (CMP process) for planarization, also generates contaminants. The contaminants resulting from the CMP process are primarily remaining slurry, organic residue etc.
The slurry may be placed between a wafer and a polishing pad and acts as a catalyzer for stimulating the polishing process during the CMP process. The slurry may continue to reside on the polished semiconductor substrate. Organic residue may also result from the polishing pad.
FIG. 1 is a schematical cross-sectional view illustrating a cleaning method performed after the conventional CMP process, and FIG. 2 is a flowchart illustrating a method of cleaning the semiconductor substrate of FIG. 1.
Referring to FIGS. 1 and 2, a device isolation layer 2 is formed at a semiconductor substrate 1 to define an active region. Thereafter, a gate pattern 6 is formed across the active region. The gate pattern 6 includes a gate insulation layer 3, a gate electrode 4, and a hardmask layer 5 which are sequentially stacked on the active region. The hardmask layer 5 is made of silicon nitride. Spacers 7 are formed on the both sidewalls of the gate pattern 6. An interlayer dielectric layer 8 is formed on an entire surface of the substrate including the spacers 7. A step difference of the interlayer dielectric layer 8 results from the gate pattern 6.
The interlayer dielectric layer 8 may be planarized by the CMP process until the hardmask layer 5 is exposed. As shown in FIG. 1, the CMP process may cause the remaining slurry A and the organic residue B (the contaminants) to be present on the interlayer dielectric layer 8. The remaining slurry A and the organic residue B are randomly located. A method of removing the remaining slurry A and the organic residue B is explained in the flowchart of FIG. 2.
First, the remaining slurry A is removed with a brush and then with diluted hydrogen fluoride (HF) at step S10. While the remaining slurry A is removed, the semiconductor substrate 1 rotates. The diluted hydrogen fluoride is a mixture of hydrogen fluoride (HF) and water (H2O) at desired rates. The use of the brush and the diluted hydrogen fluoride may cause more organic residue B.
Next, the organic residue B is removed using piranha cleaning or standard cleaning 1 (SC1 cleaning) on the substrate 1 at step S20. The piranha cleaning is a cleaning method using a solution of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) at desired rates. The piranha cleaning removes the organic residue B causing dehydrogenation and oxidation between the mixed solution and the organic residue B. The SC1 cleaning removes the organic residue B using a solution of ammonia (NH4OH), hydrogen peroxide (H2O2), and water (H2O). The substrate 1 is then rinsed with the deionized water at step S30. The scum of the organic residue B and the solutions may be removed by a rinse.
Further, a line width of the gate electrode 4 decreases as more and more highly integrating semiconductor devices are desired. Thus a resistance of the gate electrode 4 increases, so that characteristics of a semiconductor device, such as a transistor, may be degraded. To decrease the resistance of the gate electrode 4, a method of cleaning a gate electrode 4 with a tungsten layer is therefore proposed.
However, if the gate electrode 4 is made of tungsten, the organic residue B may not be removed with the piranha cleaning and the SC1 cleaning, because the tungsten may be corroded or etched by the hydrogen peroxide used in the piranha and SC1 cleaning. In other words, the hydrogen peroxide penetrates the gate electrode 4 along the interfaces between the hardmask layer 5 and the spacer 7, and may corrode or etch the gate electrode 4. Therefore, the resistance may increase with damages to the gate electrode 4. In addition, hydrogen peroxide may corrode or etch the tungsten layer to form a particle and the tungsten layer may be exposed through clamp zones on the edge of the substrate 1. The clamp zone is the edges of the substrate 1 making contact with the clamp installed in a semiconductor fabricating apparatus.
Additionally, when a contact plug or a damascene interconnection is formed by performing the CMP process to the tungsten layer, the conventional cleaning methods (i.e., the piranha and the SC1 cleaning) may not be available.